Build verification platforms, write verification automation scripts, speed up the verification process and enhance the automation of verification;

Develop, oversee and execute chip verification plans and participate in system-level verification, module-level verification and post-simulation of chips;

Solve the problems related to tools and environment during chip verification

Proficient in Linux/Unix environment, Perl/Python, C/C++ and Unix Shell;

Proficient in Verilog and System Verilog languages as well as mainstream EDA simulation tools such as VCS and Verdi;

Proficient in chip verification process and UVM verification methodology, and be able to build verification platforms using UVM + SystemVerilog;

Strong technical writing skills;

3 years or above experience as a design or verification engineer, and has participated in at least one ASIC/SOC tape-out project;

Those with the following skills are preferred;

Familiar with Ethernet physical layer protocol and serdes physical layer protocol.

Participate in the day-to-day recruitment in the Singapore branch, assist with talent recruitment, arrange interviews with candidates, etc.; 

Responsible for the personnel management of the Singapore branch, such as staff onboarding, regularization, position change and separation, maintenance and updating of staff files, signing of employment contracts, insurance payment, performance management, and staff welfare management; 

Assist in communicating and implementing the group's human resources-related policies and decisions.

Bachelor degree, major not limited;

3-5 years working experience in related fields, familiar with Singapore labor laws and regulations;

Proficient in operating office software and equipment;

Have a good sense of professionalism with strong communication skills, and work positively, proactively, carefully and conscientiously.